INVECAS Inc, a leading provider of ASIC design solutions, and Tenstorrent Inc, a leading AI/ML processor company, announced today that Tenstorrent has achieved first-pass silicon success for its recently announced Grayskull AI processor system-on-chip (SOC) utilizing INVECAS Advanced Chip Builder Tool (ACT™) physical implementation flow to achieve predictable design convergence, best-in-class PPA and accelerate time-to-tape-out for complex design.
INVECAS provides ASIC design solutions across all the technology nodes up to 6nm FINFET for key global customers targeting next generation AI, 5G, IoT, automobile and networking markets. The ASICs targeting these market applications are complex designs with multiple hierarchies featuring 1B-2B+ gate count, large number of high-speed interfaces, high performance and low power. INVECAS customers expect faster time to market for their ASIC product deployment, which drives the need for faster design convergence and a reduction in overall design cycle time from netlist to Silicon on these large designs.
INVECAS’s experienced Package and Test Design and Development team utilizes the state-of-the-art Simulation and Design tools to achieve clean signal integrity and power integrity for complex high-power products in this space. The ATE Development team is adept at fast implementation of test vectors and test methodologies to ensure reliable first pass silicon; and with key Product Engineering experience and tools we achieve industry leading metrics for high Quality and low DPPM during production.
Tenstorrent, a next-generation computing company bringing to market the first conditional execution architecture for artificial intelligence, recently announced its flagship product: Grayskull. Grayskull delivers significant baseline performance improvements on today’s most widely used machine learning models, and opens up orders-of-magnitude performance gains for current and future ML models by enabling inference and training computations to be tailored at run-time for each input presented to the model.
Tenstorrent’s architecture features an array of proprietary Tensix cores, each comprising a high utilization packet processor, high bandwidth local SRAM, a powerful, programmable SIMD and dense math computational block, and five RISC processor cores. Grayskull is a 620mm^2 chip, manufactured using Global Foundries’ 12nm process, integrating 120 Tensix cores, a 4 core ARC CPU, eight channels of LPDDR4, 16 lanes of PCI-E Gen 4 and a proprietary high performance NoC tying it all together.
“Successfully completing a large, high frequency SoC design, with significant IP-level changes occurring until late in the project, required a combination of architectural and design flow innovation, as well as a high degree of trust and collaboration between the Tenstorrent and INVECAS teams. Tenstorrent’s SoC Architecture, combined with INVECAS advanced physical implementation and DFT methodology, enabled a modular and efficient design flow, which in turn enabled us to continuously improve our core IP almost up to the point of tape-out. This was critical to our ability to deliver a truly compelling product within existing time and resource constraints,” said Drago Ignjatovic, VP of Silicon Engineering, Tenstorrent.
“Time to market is critical in a fast-paced, competitive semiconductor market. A complex design like Grayskull with 120 AI core engines in deep sub-micron technologies require innovative approach and close collaboration between the customer SOC Architects and INVECAS Physical Design Architects to carefully plan the bus connectivity, clocking and power delivery to achieve the best in class PPA target for the SOC. Flexible design methodology with ACT™ enabled independent design closure of blocks in parallel with abutted top level design style and drop in placement of newly developed AI core late in the design phase all the while ensuring predictable timing and IR convergence at full chip level,” said Srinivasa Gutta, VP of engineering, INVECAS.
“As an ASIC silicon provider INVECAS need to assure the yield and optimize the ATE test time for product with the right DFT architecture. Enabled top level glue-less DFT logic with options to test and debug single AI core or groups of AI cores in parallel to speed up test time and provide flexibility in debug and failure diagnosis. Achieved scan shift frequency of 150MHz+ with pipeline flops planned and pushed into the blocks with zero top level impact,”added Srinivasa Gutta.
